A: The microcontroller could issue a STOP condition but this may be difficult since bus contention will occur. If the micro cannot drive SDA high, there is an alternate method. The second way to abort a pending read operation is to issue clocks until a data bit value of ‘1’ occurs. A ‘1’ data bit will cause the serial FRAM to release the SDA line since it only drives low. To make this method work, the master issues an SCL rising edge, then reads the SDA line while SCL is high. If SDA is ‘0’, then another clock must be issued. If SDA is ‘1’, then the master can force SDA low while SCL is high. This is a START condition. A START condition also will cause the memory to end the read operation immediately.

See also: AN201 Interrupting a Two-Wire Read

A: 1) Speed. The “RAM” part of the F-RAM name tells us that it is a RAM, not a ROM.  Of course, EEPROM and Flash are not truly ROMs but writing to them can be very slow.  An F-RAM’s write cycles are completed immediately whereas an EEPROM/flash needs 5 to 10 ms.

2) Low Power Writes.  Writes to the F-RAM cell occur at low voltage and very little current is needed to change the data. With EEPROM and Flash, high voltages (10V charge pump) are needed and writes require 5 ms to complete a page buffer write.  The energy needed is much higher than F-RAM writes.  If E=P*t, then 5ms of write time will necessarily require 200x more energy than F-RAM.

3) High Endurance.  Writes are destructive – and floating gate devices eventually wear out; typical endurance is 100,000 to 1 million cycles. F-RAM experiences 1E12 read/write cycles or greater.

A: The 100KHz and 400KHz timing sets have been established many years ago.  We show these legacy columns to indicate that our device complies with these timing sets.  The actual timing limits of the device are shown in the 1MHz column.

A: Two-wire (I²C) is the most common and many micros implement a two-wire dedicated port.  SPI operates at much higher clock rates, up to 20MHz.  For simplicity and the use of fewer I/O micro pins, two-wire is generally used.

A: 1) Speed. The “RAM” part of the F-RAM name tells us that it is a RAM, not a ROM.  Of course, EEPROM and Flash are not truly ROMs but writing to them can be very slow.  An F-RAM’s write cycles are completed immediately whereas an EEPROM/flash needs 5 to 10 ms.

2) Low Power Writes.  Writes to the F-RAM cell occur at low voltage and very little current is needed to change the data. With EEPROM and Flash, high voltages (10V charge pump) are needed and writes require 5 ms to complete a page buffer write.  The energy needed is much higher than F-RAM writes.  If E=P*t, then 5ms of write time will necessarily require 200x more energy than F-RAM.

3) High Endurance.  Writes are destructive – and floating gate devices eventually wear out; typical endurance is 100,000 to 1 million cycles. F-RAM experiences 1E12 read/write cycles or greater.
 

A: You must issue a WREN opcode before the WRITE opcode.  The WREN opcode requires the /CS pin to go low, clock-in the opcode (06h), then /CS must return high.  The WRITE opcode then follows.  The /CS pin goes low, clock-in the opcode (02h), clock-in the address (1 or 2 bytes), clock-in the data (1 or many bytes), then /CS must return high.

See also: AN304 SPI Guide
 

A: Two-wire (I²C) is the most common and many micros implement a two-wire dedicated port.  SPI operates at much higher clock rates, up to 20MHz.  For simplicity and the use of fewer I/O micro pins, two-wire is generally used.